library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity screen is
    port (qin:in std_logic_vector(23 downto 0);
        qout:out std_logic_vector(26 downto 0);
        ring:out std_logic);
end;

architecture art of screen is
signal temp_ring:std_logic;
begin
process(qin)
begin 
    if(qin(15 downto 0)>="0000000000000000" and qin(15 downto 0)<="0000000000000101")then
        temp_ring<='1';
    else
        temp_ring<='0';
    end if;

    case qin(23 downto 20) is     
    WHEN "0000"=>fqout(26 downto 20)<="0111111"; 
    WHEN "0001"=>fqout(26 downto 20)<="0000110";    
    WHEN "0010"=>fqout(26 downto 20)<="1011011"; 
    WHEN "0011"=>fqout(26 downto 20)<="1001111"; 
    WHEN "0100"=>fqout(26 downto 20)<="1100110";     
    WHEN "0101"=>fqout(26 downto 20)<="1101101";    
    WHEN "0110"=>fqout(26 downto 20)<="1111100"; 
    WHEN "0111"=>fqout(26 downto 20)<="0000111"; 
    WHEN "1000"=>fqout(26 downto 20)<="1111111"; 
    WHEN "1001"=>fqout(26 downto 20)<="1101111";    
    WHEN OTHERS=>fqout(26 downto 20)<="0000000"; 
    end case; 
    
    fqout(19 downto 0)<=qin(19 downto 0);
    ring<=temp_ring;
end process;
end art;
